The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a resistance element and a fabrication process thereof.
The present invention covers not only a resistance element formed on a semiconductor chip, but also an integrated circuit in which such a resistance element is integrated on a common chip, together with other elements such as transistors and/or capacitors.
In semiconductor devices, resistance elements are formed generally by a patterning process of a polysilicon layer, wherein such a polysilicon layer may be formed on a diffusion region on a semiconductor substrate or on an insulation film covering the semiconductor substrate.
In order to minimize the variation of the resistance of such resistance elements, it has been practiced to minimize the sheet-resistance variation of the conductive layer from which the resistance pattern is formed. Alternatively, efforts are made to improve the precision of the patterning process.
In order to minimize the sheet-resistance variation of the conductive layer, various proposals have been made so far, including controlling of the thickness of the conductive layer or improving the quality of the conductive layer. See the Japanese Laid-Open Patent Publication 7-115173 or 9-232521.
With regard to the approach via improvement of the patterning precision of the resistance elements, there is a proposal to planarize the polysilicon layer such that the precision of the patterning is improved. See the Japanese Laid-Open Patent Publication 5-218306. Further, there is a proposal to improve the patterning precision by disposing a dummy pattern adjacent to the resistance pattern. The present invention to be described later also adopts the approach to minimize the resistance variation by improving the precision of the resistance pattern elements.
According to the foregoing approach of improving the patterning precision of the resistance, on the other hand, it has been difficult to achieve a significant improvement with regard to the resistance variation, particularly when the size of the resistance element is small. Thus, in order to avoid the foregoing problem, it has been practiced to form the resistance elements to has a relatively large size such that the variation in the patterning of the resistance element can be ignored. Such an approach, on the other hand, reduces the area of the semiconductor chip on which other elements such as transistors or interconnection patterns could otherwise have been formed. Thus, such an approach has caused an increase in the size and hence the cost of the semiconductor devices.
FIG. 1 shows an example of such a polysilicon resistance element.
Referring to FIG. 1, there is provided a number of polysilicon resistance patterns 2 on a surface of a substrate (not shown) in a parallel relationship with each other, wherein the resistance patterns 2 are connected in series by conductor patterns 4 also provided on the substrate to form a desired resistance element having a desired resistance value. In the example in which the polysilicon layer has a sheet resistance of 5Ω/□ and ten such resistance patterns 2, each having a width W of 1 μm and a length L of 100 μm, are connected in series, the resistance element thus formed shows a nominal resistance value of 5000 Ω (=5 Ω/□×(100 μm×1 μm)×10).
Thus, when the resistance patterns 2 are formed with a size tolerance of 0.1 μm, the resistance value of the resistance element may vary within a range of ±500Ω or ±10%. In order to reduce such a variation of the resistance in the resistance element, it has been necessary to increase the size W and/or L for each of the resistance patterns 2. As noted already, however, such an approach causes a decrease in the area of the semiconductor chip on which other devices are formed.